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Additional info for An Introduction to Digital Techniques: Logic gates, Flip-flops, Counters and Shift registers
CIRCUIT SYMBOL. 41. The arrow on the CK input indicates that it is positive edge triggered. That is; data enters on the positive going edge of the clock pulse. 40 Edge triggering. CK Clock pulse I I Input Data I I It \ Output Data The input Data can change part way through the clock pulse, without altering the FLIP-FLOP output. 42. This is a differentiating circuit. If the time constant (CR seconds) is much smaller than the clock pulse width, then the output waveform is a series of narrow pulses.
13. 14. --- Low Low The inputs are normally resting 'high'. 15. The Q output will go 'high', and remain so, even if the Set input returns 'high'. 16 shows a Reset command fed to the FLIPFLOP. The Q output will go 'low', and stay 'low' until a Set pulse is received. Any further Reset commands will not affect the output. Fig. 14 Reset condition: Q continually 'low'. s R Fig. 16 Activating the Reset input. - - Low High R High 39 High input activated FLIP-FLOP Set Fig. 17 Set condition: Q continually ~high'.
Part 2 introduces the basics of F LIP-FLOPS and provides a foundation for later books in this series. The FLIP-FLOP is not a new device; it has appeared in television receivers since the introduction of colour. In colour television it appears in numerous decoders where it is called a bistable. The transistor Fig. 2. 1 Low value R 1 gives a high base voltage. 7v). 2v. 2. If the collector voltage of VT2 were used to apply bias to another transistor (VT 1), it would be of an insufficient level to turn it on.