By C. Balanis [SOLUTIONS] [non-OCR]

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Normally the CLEAR input will be held HIGH when data is being received, transmitted or stored. Pin 2 is the SHIFT RIGHT SERIAL INPUT; serial data is input Manufacturer's Data 41 here, when data is to be shifted in the direction QA towards QD. Pins 3-6 inclusive are the parallel inputs enabling direct setting of the output to these inputs. Pin 7 is the SHIFT LEFT SERIAL INPUT; serial data is input here when the data is to be shifted in the direction QD towards QA. Pins 9 and 10 set the MODE of the device; whether these are HIGH or LOW decides in which of the four possible modes the register functions: (1) Inhibit the clock (often called do nothing).

Thus all the bits are shifted one bit to the right in the individual registers. This shift right action can be followed in the waveform diagrams for the remaining time allocated to the shift right mode of operation. Because the serial data input has been made LOW, then at the end of this mode's cycle all the outputs are LOW. SO is then made LOW and S1 made HIGH to prepare the register for SHIFT LEFT operation. On the next positive edge of the clock, as the SHIFT LEFT DATA input is LOW then all the outputs remain LOW.

As drawn, the switch is connected so that the input on pin 1 is connected to the output. The signals present on the select input are able to select and connect other inputs through to the output. (c) Pins 1-4 and 12-15 are the 8-input lines and are designated 10-17. Pins 9, 10, and 11 are the SELECT inputs, the selection of the input line being decided by the signals applied to the select inputs. There are three such inputs and hence 8 possible combinations of connections. Manufacturer's Data 49 Each combination will uniquely switch one of the 8 inputs to the output.

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